Typical semiconductor devices comprise multiple circuits formed within a dielectric region comprised of one or more dielectric layers on top of a silicon substrate or wafer. On top of the substrate are layers of dielectric and layers of metal and layers of metal embedded in dielectric. When the metal interconnect leads of the circuits are on different layers, conductive vias extend through the dielectric layers to make connections between the wiring leads on different interconnect levels. Sometimes, based on the circuit design, a significantly large amount of current may flow through the metal interconnect leads, causing Joule heating to increase the temperature of the metal leads. The current flowing through these leads may cause sufficient Joule heating to increase the temperature of the leads. Such temperature increases may accelerate reliability wearout mechanisms such as electromigration and stress migration that might possibly lead to failure of the integrated circuit. It is common practice to widen leads that have current densities in excess of those required for reliable operation. However, widening leads may have a deleterious impact on the area of the integrated circuit.
Current trends in integrated circuit design include using dielectric materials of increasingly low thermal conductivity, exacerbating the deleterious effects of Joule heating within the integrated circuit. In addition, as integrated circuit technologies are scaled, the number of layers of metal interconnect is increasing, making it increasingly difficult to dissipate heat from metal leads. Furthermore, integrated circuits that draw relatively large amounts of power may intensify the increases in temperature in the integrated circuit due to Joule heating effects.
During fabrication of integrated circuits, dummy metal structures may be inserted in the integrated circuit to increase the density of metal structures on the top surface of the integrated circuit. For example, insertion of dummy metal structures may lead to improved pattern consistency of metal leads and to reduced “dishing” during chemical mechanical polishing (CMP) of the integrated circuit. It is common practice to use dummy metal structures during the fabrication of integrated circuits. Because metals are much better thermal conductors than are dielectrics, the presence of dummy metal structures surrounding regions where the temperatures of metal leads may become excessive can contribute to heat flow away from such interconnect region toward heat sinking regions, thereby resulting in lower temperatures of the metal leads. Vertical vias may be formed within the dielectric layer between dummy metal structures and filled with a thermally conductive material to provide direct thermal connections between dummy metal structures. Although this may help dissipate heat from metal leads or other heat generating structures, such techniques may still be inadequate for integrated circuit applications. An integrated circuit with such heat conductive structures is described in co-pending patent application of Hunter et al. entitled “Integrated Circuit Providing Thermally Conductive Structures Substantially Horizontally Coupled To One Another Within One or More Heat Dissipation Layers To Dissipate Heat From A Heat Generating Structure”, Ser. No. 10/326,612 filed Dec. 20, 2002. This application is incorporated herein by reference.